VLSI Design

What is VLSI Design? Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. … VLSI lets IC designers add all of these into one chip. Very large-scale integration (VLSI) […]

01. NMOS devices are formed in A. p-type substrate of high doping level B. n-type substrate of low doping level C. p-type substrate of moderate doping level D. n-type substrate of high doping level Answer Option : C 02. Source and drain in nMOS device are isolated by A. a single diode B. two diodes

11. The condition for linear region is A. Vgs lesser than Vt B. Vgs greater than Vt C. Vds lesser than Vgs D. Vds greater than Vgs Answer Option : B 12. As source drain voltage increases, channel depth A. increases B. decreases C. logarithmically increases D. exponentially increses Answer Option : B 13. Speed

21. Enhancement mode device acts as switch, depletion mode acts as _____ switch A. open, closed B. closed, open C. open, open D. close, close Answer Option : A 22. Depletion mode MOSFETs are more commonly used as A. switches B. resistors C. buffers D. capacitors Answer Option : B 23. Enhancement mode MOSFETs are

31. _______ is used to deal with effect of variation A. chip level technique B. logic level technique C. switch level technique D. system level technique Answer Option : D 32. As die size shrinks, the complexity of making the photomasks A. increases B. decreases C. remains the same D. cannot be determined Answer Option

41. In nMOS device, gate material could be A. silicon B. polysilicon C. boron D. phosporus Answer Option : B 42. The commonly used bulk substrate in nMOS fabrication is A. silicon crystal B. silicon-on-sapphire C. phosporus D. silicon-di-oxide Answer Option : C 43. In nMOS fabrication, etching is done using A. plasma B. hydrochloric

51. CMOS technology is used in developing A. microprocessors B. microcontrollers C. digital logic circuits D. all of the mentioned Answer Option : D 52. CMOS has A. high noise margin B. high packing density C. high power dissipation D. high complexity Answer Option : B 53. In CMOS fabrication, nMOS and pMOS are integrated

61. N-well is formed by A. decomposition B. diffusion C. dispersion D. filtering Answer Option : B 62. ______ is sputtered on the whole wafer A. silicon B. calcium C. potassium D. aluminium Answer Option : D 63. MOS technology has more load driving capability. A. true B. false Answer Option : B 64. What

71. Advantages of E-beam masks are A. small feature size B. larger feature size C. looser layer D. complex design Answer Option : D 72. Which process is used in E-beam machines? A. raster scanning B. vector scanning C. both of the mentioned D. none of the mentioned Answer Option : C 73. What is

81. The dopants are introduced in the active areas of silicon by: a) Diffusion process b A. Diffusion process B. Ion Implantaion process C. Chemical Vapour Deposition D. Either Diffusion or Ion Implantaion Process Answer Option : D 82. To grow the polysilicon gate layer, the chemical used for chemical vapour deposition is: a A.

91. In resistive region A. Vds greater than (Vgs – Vt) B. Vds lesser than (Vgs – Vt) C. Vgs greater than (Vds – Vt) D. Vgs lesser than (Vds – Vt) Answer Option : B 92. Threshold voltage is negative for A. nMOS depletion B. nMOS enhancement C. pMOS depletion D. pMOS enhancement Answer